1. Field of the Invention
This invention relates, in general, to methods for fabricating semiconductor devices and, more particularly, to an improved method for self-aligned fabrication of semiconductor devices.
2. Background Art
The packing density, complexity and size of semiconductor devices and integrated circuits depends greatly upon the minimum size devices which may be achieved during fabrication. The smaller the individual semiconductor devices that can be fabricated, the larger the number of devices that can be accommodated within a given semiconductor area, and the greater circuit complexity that can be achieved. Further, smaller devices consume less power and generally also provide greater speed. Thus, there is an ongoing desire in the semiconductor device and integrated circuit art to fabricate ever smaller semiconductor devices, particularly transistors.
Most transistors, and particularly those contained within integrated circuits, are fabricated using lithographic techniques. The area occupied by a particular transistor depends, among other things, upon the minimum size opening which may be replicated in the structure and the alignment tolerance which must be provided to permit registration of successively applied lithographic patterns. For most transistor structures in integrated circuits and the like, a number of successive masking layers must be applied. The cumulative alignment tolerance associated with the successive layers adds substantially to the area occupied by the transistor, even though the transistor utilizes openings of minimum resolvable width. Accordingly, there is an ongoing need in the semiconductor device and integrated circuit art for improved manufacturing methods which minimize the alignment tolerance requirements of the manufacturing process. Thus, it is an object of the present invention to provide an improved manufacturing method for semiconductor devices and integrated circuits having reduced alignment tolerance requirements.
It is a further object of the present invention to provide an improved method for fabricating semiconductor devices and integrated circuits, wherein certain critical device regions are self-aligned
It is an additional object of the present invention to provide an improved method for fabricating multiterminal semiconductor devices and integrated circuits wherein at least one active device region, at least three device terminals, and an isolation wall surrounding the device are self-aligned.
It is a still further objective of the present invention to provide an improved method for fabricating bipolar transistors and integrated circuits wherein the emitter, and emitter contact, base contact and collector contact, and a surrounding isolation wall are self-aligned. aligned.
It is a still additional object of the present invention to provide an improved method for fabricating semiconductor devices and integrated circuits wherein self-alignment of certain critical device regions is provided by a single master mask.
It is a still further object of the present invention to provide a means for fabricating semiconductor devices and integrated circuits using a single master mask for defining critical device regions which is especially suitable for devices having lateral geometries in the micron to submicron range.
As used herein, the words "master mask" are used to refer to a single mask, however provided, which contains the images of device regions whose lateral alignment and spacing must be fixed with precision.
As used herein the words "block-out mask" or "selector mask" are intended to refer to a mask used during the process of manufacture of a semiconductor device or integrated circuit in conjunction with the master mask. The purpose of the block-out or selector mask is to cover certain openings of the master mask while exposing others. It is not a high precision mask in that it need not have dimensions which exactly match or exactly register with images in the master mask, and need not be precisely aligned to the images in the master mask. The openings in the master mask are used to size and locate critical device regions, whereas the open and covered portions of the block-out or selector masks are used merely to uncover or cover particular openings in the master mask. Those of skill in the art will understand how such block-out and/or selector masks are used.